1. Field
Example embodiments disclosed herein relate to methods of fabricating a semiconductor device, and more particularly, to methods of fabricating a contact plug of a semiconductor device.
2. Description of Related Art
As semiconductor devices become more highly integrated, various techniques for achieving higher integration are being proposed. For electrical connection between a capacitor and a bit line and between source/drain regions, a self aligned contact (SAC) technique is used.
In the SAC technique, after forming an opening that simultaneously exposes gates of a region requiring a contact plug and a semiconductor substrate between the gates, a conductive layer is deposited to fill the opening. The contact plug is formed by planarizing the conductive layer. Subsequently, the capacitor and the bit line, electrically connected to the contact plug, are formed.
If the contact plug of the semiconductor device is formed using the SAC technique, an etch selectivity between an interlayer insulation layer (covering a semiconductor substrate) and a capping pattern (covering a gate electrode) may not be satisfactory during the formation of the opening. Thus, the top height and sidewall thickness of the capping pattern may be insufficient. If over etching is performed to prevent Not Open (N/O) of the semiconductor substrate between the gates during the formation of the opening, the thickness of a shoulder portion between the top portion (or upper surface) and sidewall of the capping pattern may become weaker. If a bar type contact plug is formed, it becomes difficult to control planarization of the conductive layer as a removal rate (RR) of an etch region increases. Accordingly, leakage may occur more frequently between the gate electrode and the contact plug.
An additional plug connected to the contact plug may be formed subsequent to formation of the contact plug. If the over etching is performed during the process for forming the additional plug connected to the contact plug, the shoulder portion of the capping pattern may be further etched. If the shoulder portion of the capping pattern is further etched, the additional plug and the gate electrode are electrically connected to each other. As such, the semiconductor device cannot operate.
As a design rule is reduced due to the higher integration of the semiconductor devices, the above-mentioned limitations reduce a shoulder margin of the capping pattern (e.g., a manufacturing margin for forming the contact plug of the semiconductor device).